The present invention relates to a semiconductor device, and in particular, to a technique applicable to a semiconductor device including, for example, a transistor and wiring.
One type of semiconductor devices has a transistor for power control. Such a semiconductor device is described, for example, in Japanese Unexamined Patent Publication No. 2001-77206. The above Unexamined Patent describes that a plurality of transistor cells are arranged in parallel to each other. In detail, a plurality of transistors is provided in parallel to each other in each transistor cell. Drain wiring and source wiring are pulled out from each transistor so as to be oriented in directions opposite to each other. Members to be coupled to the drain wiring and those to be coupled to the source wiring are both arranged between the transistors cells.
On the other hand, transistors each using a compound semiconductor layer as a channel are recently under development. This transistor has a characteristic that an on-resistance is low.